This invention relates to integrated inductors on Integrated Circuits (ICs) and in particular to ICs manufactured with modern fine-line CMOS processes that are capable of operating at a frequency of several GHz.
Integrated inductors are being integrated into ICs because modern fine-line CMOS processes are capable of operating at a frequency of several GHz. The processes and technology are readily available from multiple foundry sources to achieve this level of performance. Accordingly, many design engineers at “fabless” semiconductor companies, design integrated “on-chip” inductors into ICs that operate at high frequencies.
One of the drawbacks of prior art “on-chip” inductors is the low Q, or quality factor, of the integrated inductor. The low Q limits the performance of the integrated inductors. One reason for this low Q is the unwanted dissipation of energy in the semiconductor substrate as is discussed in Yue, et al. A Physical Model for Planar Spiral Inductors on Silicon, Int. Electron Devices Meet. Tech. Digest, December 1996, 196, pp. 155–158; which is incorporated herein by reference.
Various techniques for increasing Q have been tried, including the use of substrate material having a high resistivity, see Ashby, et al., High-Q Inductors for Wireless Applications in a Complementary Silicon Bipolar Process, IEEE Journal of Solid-State Circuits, vol. 31, pp. 4–9, January 1996; also incorporated herein by reference. Etching a pit or trench below the inductor was discussed in Chang, et al., Large, Suspended Inductors on Silicon and Their Use in a 2-mm CMOS RF Amplifier, IEEE Electron Device Letters, vol. 14, pp. 246–248, May 1993, and using a ground shield between the inductor and the substrate was discussed in Yue, et al., On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's, IEEE Journal of Solid-State Circuits, vol. 33, pp. 743–751, May 1998; Rofougaran et al., A 1 GHz CMOS RF Front-End for a Direct Conversion Wireless Receiver, IEEE Journal of Solid-State Circuits, vol. 31, pp. 880–889, July 1996; and Tsukahara et al., A 2 GHz 60 dB Dynamic-Range Si Logarithmic/Limiting Amplifier with Low-Phase Deviations, in Int. Solid-State Circuits Conf. Dig. Tech. Papers, February 1997, pp. 82–83; all of which are incorporated herein by reference.
Another technical reference which discusses some limitations of real-world integrated circuit inductors is On-Chip RF Spiral Inductors and Bandpass Filters Using Active Magnetic Energy Recovery, by Wu and Chang, was published in the Proc. IEEE Custom Integrated Circuits Conference, May 2002, pp. 275–278. This paper discusses an active circuit which may be used to enhance the Q of integrated circuit inductors. It does not address the issue of increasing the operating frequency of the inductor circuit.
U.S. Pat. No. 6,233,012 granted May 15, 2001, is entitled Parasitic Capacitance Reduction for Passive Charge Read-Out by Guerrieri et al. describes a integrated circuit with a driven shield underneath a sensitive lead that has some finite capacitance. This reference shows that the capacitance to the shield underneath can be made to effectively be eliminated by using a unity-gain amplifier to drive the shield. In this reference, the sensitive lead is at an equipotential, and so is the shield. So even though this sensitive lead may cover some significant physical area, a single shield, of one potential, is adequate to cancel the oxide capacitance of interest.
The article On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's, shows that a solid metal sheet below the inductor provides shielding from the substrate, but incurs losses due to induced eddy currents. This reference also shows that by cutting small slits in the otherwise continuous metal sheet below the inductor, the losses due to these eddy currents may be eliminated and the overall inductance and quality factor of the inductor may be improved. While this technique offers some improvements (a reported 33% improvement in the Q at 2 GHz), the bottom plate is in close proximity to the relatively large surface area of the inductor, and as such forms a parallel-plate capacitor with significant capacitance. This capacitance reduces the self-resonant frequency, and can limit the overall frequency performance. However, as mentioned at page 749 of the article, there are almost no substrate losses.
Therefore it is desired to have an integrated inductor that does not have significant substrate losses, and one which has a high self-resonant capacitance, thus allowing very high frequency performance.